module counter(rst, clk, count);
   parameter WIDTH = 4;
   input rst;
   input clk;
   output reg [WIDTH-1:0] count;

   always@(posedge clk or posedge rst)
     begin
	if(rst) 
	  count <= 0;
	else
	  count <= count + 1;
     end
endmodule // counter

